INTENA
The Interrupt Enable register lets you read and set a bit mask that disables or enables interrupts in the Amiga. This information is also valid for INTREQ and their read-only equivalents INTENAR and INTREQR.| Bit | Function | Description |
|---|---|---|
| 15 | SET/CLR | 0=clear, 1=set bits that are set to 1 below |
| 14 | INTEN | Enable interrupts below (master toggle) |
| 13 | EXTER | Level 6 External interrupt |
| 12 | DSKSYN | Level 5 Disk Sync value found |
| 11 | RBF | Level 5 Receive Buffer Full (serial port) |
| 10 | AUD3 | Level 4 Audio Interrupt channel 3 |
| 09 | AUD2 | Level 4 Audio Interrupt channel 2 |
| 08 | AUD1 | Level 4 Audio Interrupt channel 1 |
| 07 | AUD0 | Level 4 Audio Interrupt channel 0 |
| 06 | BLIT | Level 3 Blitter Interrupt |
| 05 | VERTB | Level 3 Vertical Blank Interrupt |
| 04 | COPER | Level 3 Copper Interrupt |
| 03 | PORTS | Level 2 CIA Interrupt (I/O ports and timers) |
| 02 | SOFT | Level 1 Software Interrupt |
| 01 | DSKBLK | Level 1 Disk Block Finished Interuppt |
| 00 | TBE | Level 1 Transmit Buffer Empty Interrupt (serial port) |
You set and clear bits in the same way as you do for DMACON. Learn more about interrupt programming on winnicki.net.